Freelance · Firmware · FPGA · Drivers · SDKs

Embedded and FPGA development for demanding systems

I develop firmware, FPGA designs and low-level software – including the drivers and SDKs that connect your hardware to the PC and the application. From prototype bring-up to verification.

More than 20 years of project experience in space, avionics, medical technology, research and industrial automation.

Discuss your project See project examples

Services

Where I can support you – from individual components to development of the complete system.

Firmware development

Firmware for microcontrollers and embedded processors – bare-metal, on an RTOS or on embedded Linux.

  • Device firmware including control of peripherals, sensors and actuators
  • Bootloaders and U-Boot
  • Cross toolchains and driver adaptations for embedded Linux
  • ARM Cortex-M/A
  • STM32
  • NXP
  • Microchip/Atmel
  • FreeRTOS
  • Zephyr
  • C/C++
  • Python

FPGA and IP core development

Digital logic in VHDL – from a single IP core to a complete FPGA design, including SoC FPGAs.

  • IP cores to a requirements specification, with testbenches
  • Signal processing in the FPGA with Vitis HLS, e.g. FFT-based OCT reconstruction
  • Fast data paths, e.g. JESD204B for ADCs and DACs above 1 GHz
  • Designs for space-grade FPGAs (RTAX antifuse)
  • VHDL
  • Vitis HLS
  • AMD/Xilinx
  • Intel/Altera
  • Microchip/Microsemi
  • Virtex UltraScale
  • Zynq 7000
  • Nios
  • MicroBlaze

Interfaces, drivers and SDKs

The link between hardware and application: high-speed and industrial interfaces plus the software on the host side.

  • USB 3 connectivity, e.g. via Cypress FX3 or FTDI FT60x
  • PCI Express with DMA and a Windows driver (WDF)
  • Host drivers for Linux and Windows, SDKs for application integration
  • USB 3.1 Gen 1
  • PCIe
  • EtherCAT
  • Profinet
  • Modbus
  • RS-485
  • IEEE 802.15.4

Bring-up and debugging

Getting new hardware running and narrowing down the causes of faults – at board, logic and software level.

  • Prototype bring-up
  • Hardware debugging and signal analysis with measurement and test equipment
  • System integration of FPGA, firmware and host software
  • Bring-up
  • Debugging
  • Signal analysis
  • System integration

Test systems and verification

Showing that a design meets its requirements – in simulation and on the hardware.

  • Requirements validation, formally and with testbenches
  • Simulation and verification, e.g. with ModelSim
  • Test systems and hardware-in-the-loop simulation of sensors
  • ModelSim
  • Testbenches
  • HIL
  • Requirements engineering

Joining ongoing development

Support for existing teams and products – getting up to speed with your requirements, source code and processes.

  • Work on subsystems of larger projects, e.g. in space and avionics
  • Adapting existing drivers and toolchains
  • Working in the V-model, to DO-254 or agile with Scrum
  • V-model
  • DO-254
  • Scrum

Embedded AI on microcontrollers

Running trained models directly on the device – on the microcontroller and its NPU, without a cloud connection.

  • Image data classification on a microcontroller NPU, e.g. NXP MCXN947
  • Integrating TensorFlow Lite models into device firmware
  • In practice: part of the HSCAM NANO camera
  • TensorFlow Lite
  • NPU
  • NXP MCXN947
  • Image classification
  • Edge inference

Functional safety

For safety-related development I bring certification as a Functional Safety Engineer, knowledge of the relevant standards and project experience.

Qualification

  • Certified Functional Safety Engineer (TÜV Rheinland)

Standards knowledge

  • IEC 61508
  • ISO 13849
  • ISO 26262
  • DO-254

Project experience

  • Concept and software development for a safety-related assembly to ISO EN 13849, Performance Level d
  • FPGA development for avionics projects to DO-254

Project examples

Task, my contribution and the technologies used – selected projects from industry, medical technology, space and avionics.

HSCAM STREAMER camera mounted in a test rig with a linear stage and connected measurement and data cables
STREAMER 1M13 in a test rig with a linear stage
Rear panel of the camera with connectors for power, GPIO, trigger/sync, ADC and USB 3.0
Connectors: power, GPIO, trigger/sync, ADC, USB 3.0
Demonstration setup at a high-speed shear, with a red HSCAM camera in the lower right
Demonstration setup at a high-speed shear

Photos: HSCAM GmbH

Own product development · Industrial imaging

HSCAM STREAMER – a high-speed camera that records continuously

The camera is developed and sold by HSCAM GmbH in Leipzig. I am one of the company's two managing directors.

Task
A high-speed camera for production lines in continuous operation: it should record without interruption and tie measurement values to the exact frame they belong to – instead of writing short sequences into internal memory.
Technical challenge
At 1,280 × 864 pixels and around 1,300 frames per second the sensor produces about 1.44 GB/s. This has to be reduced in real time to a data stream that USB 3.0 can carry continuously.
My contribution
  • Product development across the complete system
  • FPGA design for the real-time image processing on Altera/Intel FPGAs
  • USB 3 interface via Cypress FX3 – FX3 firmware and the matching FPGA IP core
  • Optimizing robustness and throughput to a continuous 300 MB/s
  • Driver and SDK infrastructure on the PC and a Python wrapper
Result
  • STREAMER 1M13 is available: 1,280 × 864 px at 1,318 fps continuously, up to 168,000 fps with a reduced region of interest
  • Edge-preserving in-camera compression of about 5:1 to around 300 MB/s over USB 3.0
  • 4 × 16-bit ADC and 2 × GPIO captured on the same clock as every frame
  • Designed for 24/7 operation and demonstrated around the clock in a steel-mill installation
  • Altera/Intel FPGA
  • Quartus
  • Qsys
  • Real-time image processing
  • Compression
  • USB 3.0
  • Cypress FX3
  • Driver and SDK
  • Python
  • Synchronized data acquisition
STREAMER 1M13 on hscam.com

HSCAM NANO: image classification on a microcontroller

Part of the HSCAM NANO is the classification of image data directly on the NPU of an NXP MCXN947, implemented with TensorFlow Lite.

  • NXP MCXN947
  • NPU
  • TensorFlow Lite
  • Embedded AI
Medical technology

Retinal OCT – FPGA signal processing from ADC interface to 3D dataset

I was responsible for the FPGA design of a prototype for a medical product that diagnoses the retina using optical coherence tomography (OCT). The prototype is intended for use in a clinical study. OCT produces high-resolution, contact-free cross-sectional images of the retinal layers.

Illustration: OCT B-scan of the retina with a marked cut line and the matching A-scan, the intensity profile over depth
Task
FPGA design based on Virtex UltraScale: acquiring the measurement data, driving the MEMS scanner and processing the OCT data all the way to the finished 3D dataset of the retina – entirely inside the FPGA.
Technical challenge
Three JESD204B dual ADCs, each sampling at 1 GHz, deliver the raw data for four parallel OCT data streams and a k-clock signal used to linearize the laser sweep. The partly very complex algorithms had to be parallelized and implemented so resource-efficiently that the entire processing chain fits into the FPGA.
My contribution
  • Responsible for the FPGA design on Virtex UltraScale
  • Planning and bring-up of the hardware assembly as an FMC daughterboard for the AMD VCU108 development board
  • Interfacing three JESD204B dual ADCs, each at 1 GHz sample rate
  • DDR4 memory interface
  • MEMS scanner control
  • IP core in Vitis High Level Synthesis (HLS) for parallel processing of four OCT data streams – a pipeline including k-clock resampling, dispersion compensation, Fast Fourier Transform (FFT) and OCT reconstruction
  • Parallelizing the algorithms and optimizing FPGA resource usage
  • Building the 3D dataset inside the FPGA
  • USB 3 interface via FTDI FT60x for configuration and data streaming to the PC, including driver and SDK infrastructure and a Python API
  • AMD/Xilinx
  • Virtex UltraScale
  • Vivado
  • Vitis HLS
  • JESD204B
  • FMC
  • VCU108
  • FFT
  • DDR4
  • USB 3.0
  • FTDI FT60x
  • Python API
  • MEMS scanner
  • OCT
  • Retinal imaging
Space

METimage – FPGA design and test systems for a space instrument

METimage is a multi-spectral imaging radiometer for use in space. I contributed to its development as a supplier within the supply chain.

Task
Logic for a space-grade RTAX antifuse FPGA and test systems for the associated electronics.
Technical challenge
Antifuse FPGAs can only be programmed once, so the design has to be fully verified before programming.
My contribution
FPGA design for the RTAX antifuse FPGA and development of the associated test systems.
  • RTAX antifuse FPGA
  • VHDL
  • Test systems
  • Space-grade
Avionics

Power management system and brake control unit for a military/transport aircraft

Contribution to the FPGA development for two avionics units: a power management system and a brake control unit.

Task
Implementing the FPGA functions to the requirements specification.
Technical challenge
Development to DO-254: every requirement has to be implemented and verified traceably.
My contribution
Requirements engineering, IP core development in VHDL and extensive verification with ModelSim.
  • Microsemi/Actel FPGA
  • VHDL
  • ModelSim
  • DO-254

More projects

Industrial

Heating control and pressure maintenance systems

Firmware for distributed, networked controllers including valve and pump control.

  • STM32
  • Firmware
  • Distributed systems
Functional safety

Safety-related assembly to ISO EN 13849

Concept and software development for an assembly required to meet Performance Level d.

  • ISO EN 13849
  • PL d
  • Software
Simulation

Hardware-in-the-loop simulation of sensors

Circuit simulation of sensors with programmable logic for electrically powered aircraft.

  • CPLD design
  • USB
  • HIL
Broadcasting

FPGA-based broadcasting coders

Contribution to the development of several coders, including DAB+, ISDB-T and ISDB-T MM.

  • FPGA
  • DAB+
  • ISDB-T
Drivers

Windows drivers for PCIe and USB

A WDF driver for an FPGA board connected via PCI Express and an HID mapper driver (WDF) for game controllers over USB 2.0.

  • WDF
  • PCIe
  • USB HID
Wireless

IEEE 802.15.4 radio systems

Several radio systems (ZigBee) in the 2.4 GHz and 868 MHz ISM bands with star and point-to-point topologies.

  • IEEE 802.15.4
  • ZigBee
  • ISM band

Working together

How a project gets started.

  1. Inquiry

    You briefly describe the task, the existing hardware and the support you need – by e-mail or phone.

  2. Technical clarification

    We discuss requirements, interfaces and constraints and define the scope.

  3. Proposal

    Based on the agreed scope you receive a proposal for the approach and effort.

  4. Implementation

    Development in coordination with you. I hand over the results in the agreed form.

I adapt to existing development processes, such as the V-model, DO-254 or Scrum. Projects can be run in English or German.

About me

I am a development engineer (Master of Science in Computer Science) and have been developing embedded systems for more than 20 years. My focus is FPGA design, firmware and connecting hardware to host systems through drivers and SDKs.

My projects come from space, avionics, medical technology, research and industrial automation – from work on individual components to product development across the complete system. As M.Rick Engineering I offer these services as a freelance engineer (contractor) based in Leipzig, Germany. I am also a managing director of HSCAM GmbH.

Other projects of mine include hscam.com, reise.surfcenter-leipzig.de and the-party-police.de.

Qualifications

  • Master of Science in Computer Science
  • Functional Safety Engineer (TÜV Rheinland)

Industries

  • Aerospace
  • Research and science
  • Industrial automation
  • Medical technology

Development processes

  • V-model
  • DO-254
  • Agile (Scrum)

Discuss your project

Send me an e-mail or give me a call. A short description is enough to get started.

M.Rick Engineering

Matthias Rick, M.Sc.

E-mail [email protected]
Phone +49 173 3 555 979
Biedermannstraße 88
04277 Leipzig
Germany

What helps with an inquiry

These details help me understand your project quickly. Anything still open we can clarify together.

  1. TaskWhat should be developed, extended or investigated?
  2. Existing hardwareBoards, microcontrollers or FPGAs, interfaces
  3. Support needede.g. development, bring-up, verification or joining your team
  4. TimeframePlanned start and key dates
Prepare an e-mail inquiry